A data driver of a flat display panel converts digital video data into analog video data and transfers the analog video data to a display panel. A digital-to-analog converter (DAC) occupies a large area of the entire structure of the data driver, and there have been diverse attempts to reduce the area of the digital-to-analog converter. Among them is a lamp-type digital-to-analog converter using time variant signals (TVS), which is regarded as an alternative.
A lamp-type digital-to-analog converter is driven by receiving a time variant signal representing a plurality of grayscale voltages and selects and outputs a particular grayscale voltage.
FIG. 1A is a block diagram snowing major parts of a conventional driver using a single time variant signal. A driver using a single time variant signal is disclosed in U.S. Pat. No. 5,440,256, entitled “Dual Mode Track and Hold Drivers for Active LCD's.”
Referring to FIG. 1, the driver using a single time variant signal includes a single TVS generator 110, an N-bit switch 120, an N-bit pulse signal generator 130, and a channel buffer 140. The single TVS generator 110 generates a single time variant signal sequentially representing all grayscale voltages at every period of one line time. The N-bit switch 120 receives the single time variant signal and performs switching onto the single time variant signal to select a grayscale voltage corresponding to video data. The N-bit pulse signal generator 130 controls the N-bit switch 120. The channel buffer 140 outputs an output of the N-bit switch 120 through a source line.
The N-bit switch 120, the N-bit pulse signal generator 130 and the channel buffer 140 are some of the constituent elements of a channel block of the driver, and they are provided to every channel block constituting the driver. The single TVS generator 110 is shared by all channels.
FIG. 1B illustrates an operation of the driver using a single time variant signal. The single TVS generator 110 is synchronized with a clock signal and generates a time variant signal 160 sequentially representing 2N grayscale voltages for a one line time. The time variant signal 160 is inputted to the N-bit switch 120 of each channel. The N-bit pulse signal generator 130 generates an N-bit pulse signal 170. The N-bit switch 120 selects a particular grayscale voltage among the grayscale voltages of the time variant signal 160 by being turned on/off according to one pulse signal among 2N pulse signals. A grayscale voltage signal 180 selected by the N-bit switch 120 is transferred to a source line of the display panel through the channel buffer 140.
Since the digital-to-analog converter using a single time variant signal sequentially represents 2N grayscale voltages for one line time, the digital-to-analog converter is short of time for charging a panel load. Thus, there is an error between the voltages of pixels. Moreover, much power is consumed when the pulse signal generators of all channels operate in synchronization with a clock signal. Also, since a switch and an N-bit pulse signal generator are added to each channel, a channel area is increased. These problems become morn serious as a display device has high grayscale, high definition and large size.
FIG. 2A is a block diagram showing major parts of a conventional driver using a plurality of time variant signals. A driver using the plurality of time variant signals is disclosed in Korean Patent No. 727,410, entitled “Digital-to-Analog Converting Circuit and Method for Driving a Flat Display Panel Using Multi-Ramp Signals.”
A driver using the plurality of time variant signals is suggested to resolve the above-mentioned problems. The driver includes a multiple TVS generator 210, an M-bit switch 220, an (N-M)-bit pulse signal generator 230, and a channel buffer 240.
The multiple TVS generator 210 divides a region of all grayscale voltages into (½M) grayscale voltage regions for every period of one rue time and generates a plurality of (2M) time variant signals. The M-bit switch 220 receives the plurality of the time variant signals and performs switching onto the plurality of the time variant signals to select a grayscale voltage, corresponding to video data. The channel buffer 240 outputs an output of the M-bit switch 220 to a source line of the display panel. Herein, N and M are positive integers and N is greater than M (N>M).
The M-bit switch 220, the (N-M)-bit pulse signal generator 230, and the channel buffer 240 are some of the constituent elements of a channel block of the driver and they are provided to every channel constituting the driver. The multiple TVS generator 210 is shared by the channels.
FIG. 2B illustrates an operation of the driver using the plurality of time variant signals.
The multiple TVS generator 210 generates a plurality of time variant signals 260. Since the plurality (2M) of the time variant signals 260 represent all grayscale voltages by regions, each time variant signal 260 sequentially represents 2N-M grayscale voltages for a period of one line time.
The plurality (2M) of the time variant signals 260 are inputted to the M-bit switch 220 of each channel. The (N-M)-bit pulse signal generator 230 generates 2N-M pulse signals 270. The M-bit switch 220 selects a particular grayscale voltage among the grayscale voltages of the time variant signals by being turned on/off according to one of the pulse signals among the 2N-M pulse signals 270. A grayscale voltage signal 280 selected by the M-bit switch 220 is transferred to a source line of the display panel through the channel buffer 240.
When a plurality of time variant signals are used, the display panel charge time is increased as much as 2M. Thus, it is possible to reduce an error between pixel voltages. Also, since a clock frequency that is 2M times as slow is used, power consumption may be reduced. In addition, since a circuit of the (N-M)-bit pulse signal generator 230 is reduced into (N-M) bits, a channel area is reduced as well.
However, each channel includes a counter which is formed of a plurality of flip-flops and the (N-M)-bit pulse signal generator 230 which is formed of multiple logic circuits, the digital-to-analog converter still occupies a large area. Moreover, a great deal of power is still consumed when the (N-M)-bit pulse signal generators of all channels operate in synchronization with a clock signal.